3 September 2010, 6:02 am
( University of California - Los Angeles ) A UCLA team led by Xiangfeng Duan has developed a new fabrication process for high-speed graphene transistors using a nanowire as the self-aligned gate. This new technique does not produce any appreciable defects in the graphene during fabrication, so the carrier mobility is retained. Also, by using a self-aligned approach with a nanowire as the gate ...... Read More »